LAN83C171 Ver la hoja de datos (PDF) - SMSC -> Microchip

Número de pieza

componentes Descripción

Lista de partido

LAN83C171

EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller

SMSC -> Microchip 

TABLE OF CONTENTS

FEATURES ........................................................................................................................................1

GENERAL DESCRIPTION .................................................................................................................2

PIN CONFIGURATION.......................................................................................................................5

DESCRIPTION OF PIN FUNCTIONS .................................................................................................6

FUNCTIONAL DESCRIPTION..........................................................................................................10

PCI INTERFACE..........................................................................................................................12

TRANSMIT/RECEIVE ARBITRATION FOR PCI BUS .................................................................12

SYSTEM ERRORS ......................................................................................................................12

BIG/LITTLE ENDIAN SUPPORT ..................................................................................................12

POWER DOWN MODE ....................................................................................................................14

DMA OPERATION .......................................................................................................................14

TRANSMIT DMA..............................................................................................................................14

Direct Queuing Method.................................................................................................................14

Fragment List Method ..................................................................................................................16

Interrupting Transmit Chain..........................................................................................................18

Transmit Buffer Full .....................................................................................................................18

Transmit Underrun .......................................................................................................................18

Exception to Underrun ReTransmission........................................................................................18

Maximum Transmit Size and Burst Rate.......................................................................................18

RECEIVE DMA.................................................................................................................................19

Free Buffer Pool Method...............................................................................................................19

Adding Receive Buffers to the Pool...............................................................................................20

Receive Lookahead Method .........................................................................................................20

Stopping the Receive DMA...........................................................................................................25

Maximum Receive Size and Burst Rate ........................................................................................25

MAC OPERATION ...........................................................................................................................26

MII MANAGEMENT INTERFACE .................................................................................................32

EEPROM INTERFACE.................................................................................................................32

JUMPER OPTIONS (EEPROM/RAM)...........................................................................................33

Advanced Configuration and Power Interface (ACPI) Support .......................................................33

Wake-Up Events and Notification .................................................................................................33

EPIC Power States.................................................................................................................34

D3(Cold1) Software Driver Requirements .....................................................................................35

Supporting Power Management Options.......................................................................................35

PME Generates a PCI Bus Interrupt .............................................................................................35

Initial Power-On Reset (POR).......................................................................................................35

Special Power Management Mode................................................................................................36

POWER DOWN MODE ...............................................................................................................36

SOFT RESET ..............................................................................................................................37

CONFIGURATION ...........................................................................................................................37

Mapping of Control Functions.......................................................................................................37

Mapping of Flash RAM Functions.................................................................................................37

DMA DESCRIPTOR BITS DESCRIPTION........................................................................................39

TRANSMIT DMA DESCRIPTOR BITS DESCRIPTION .................................................................39

RECEIVE DMA DESCRIPTOR BITS DESCRIPTION....................................................................41

CONTROL REGISTER MAP/REGISTERS DECODE........................................................................43

CONFIGURATION REGISTERS MAP..............................................................................................44

3

Share Link: