COM20051ILJ Ver la hoja de datos (PDF) - SMSC -> Microchip

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COM20051ILJ

Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

SMSC -> Microchip 

ALE

ADDRESS

DECODING

CIRCUITRY

AD0-AD7

1K x 8

RAM

ADDITIONAL

REGISTERS

nINTR

nRESET IN

nRD

nWR

nCS

STATUS/

COMMAND

REGISTER

RESET

LOGIC

MICRO-

SEQUENCER

AND

WORKING

REGISTERS

BUS

ARBITRATION

CIRCUITRY RECONFIGURATION

TIMER

TX/RX

LOGIC

nPULSE1

nPULSE2

nTXEN

RXIN

20 MHz

or 40MHz

CORE CLOCK

NODE ID

LOGIC

FIGURE 9 – ARCNET CORE BLOCK DIAGRAM

SMSC DS – COM20051I

Page 22

Rev. 03/27/2000

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