AT89S4D12-12JC Ver la hoja de datos (PDF) - Atmel Corporation
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AT89S4D12-12JC Datasheet PDF : 13 Pages
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AT89S4D12
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 1
Port 1 is a 5-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
In addition, P1.0, P1.1, and P1.3 can be configured as the
SPI data output, data input and shift clock input pins, as
shown in the following table.
Port Pin
P1.0
P1.1
P1.3
Alternate Functions
SDO (data output pin for SPI channel)
SDI (data input pin for SPI channel)
SCK (clock input pin for SPI channel)
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
TEST1
TEST1 is set to VCC during downloading of the Flash pro-
gram or data memory. This pin can be left unconnected or
tied to ground during normal operation.
TEST2
Test input. This pin has no user available function and can
be left unconnected or tied to ground.
Special Function Registers
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Memory Control Register The MCON register contains
the RDY/BSY flag and the most significant Flash address
bit A16, for the 128K bytes of on-chip Flash data memory.
SPI Registers Control and status bits for the Serial Periph-
eral Interface are contained in registers SPCR (shown in
Table 3) and SPSR (shown in Table 4). The SPI data bits
are contained in the SPDR register. Writing the SPI data
register during serial data transfer sets the Write Collision
bit, WCOL, in the SPSR register. The SPDR is double buff-
ered for writing and the values in SPDR are not changed by
Reset.
Dual Data Pointer Registers To facilitate data transfer,
two banks of 16-bit Data Pointer Registers are provided:
DP0 at SFR address locations 82H - 83H and DP1 at 84H -
85H. Bit DPS = 0 in SFR MCON selects DP0 and DPS = 1
selects DP1. The user should always initialize the DPS bit
to the appropriate value before accessing the respective
Data Pointer register.
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