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AT89S4D12-12JC

8-Bit Microcontroller with 132K Bytes Flash Data Memory

Atmel Corporation 

AT89S4D12

Table 2. MCON—Memory Control Register

MCON Address = 96H

-

-

-

-

Bit

7

6

5

4

Reset Value = XXXX X010B

-

DPS

RDY/BSY

A16

3

2

1

0

Symbol

DPS

RDY/BSY

A16

Function

Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register,

DP0, and DPS = 1 selects the second bank, DP1.

DataFlash Ready/Busy Flag. This bit serves as the RDY/BSY flag in a Read-Only mode

during DataFlash write. RDY/BSY = 1 means that the DataFlash is ready to be

programmed. While programming operations are being executed, the RDY/BSY bit

equals `0' and is automatically reset to `1' when programming is completed.

Memory Block Select. A16 = 0 selects the lower 64K bytes DataFlash memory block.

A16 = 1 selects the upper 64K bytes DataFlash block.

Table 3. SPCR—SPI Control Register

SPCR Address = D5H

Reset Value = 000X 01XXB

SPIE

SPE

DORD

-

CPOL

CPHA

SPR1

SPR0

Bit

7

6

5

4

3

2

1

0

Symbol

SPIE

SPE

DORD

CPOL

CPHA

SPR0

SPR1

Function

SPI Interrupt Enable. This bit, enables SPI interrupts: SPIE = 1 enable SPI interrupts. SPIE = 0 disables

SPI interrupts.

SPI Enable. SPI = 1 enables the SPI channel and connects SDO, SDI and SCK to pins P1.0, P1.1, and

P1.3. SPI = 0 disables the SPI channel.

Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data

transmission.

Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is

low when not transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.

Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between

master and slave. Please refer to figure on SPI Clock Phase and Polarity Control.

SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1

and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency,

FOSC., is as follows:

SPR1

0

0

1

1

SPR0

0

1

0

1

SCK = FOSC. divided by

4

16

64

128

4-285

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