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CY62148V Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza
componentes Descripción
Lista de partido
CY62148V
Cypress
Cypress Semiconductor Cypress
CY62148V Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
PRELIMINARY
CY62148V
AC Test Loads and Waveforms
R1 1800
5V
R1 1800
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
R2
990
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
990
62148V-2
3.0V
GND
3ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
639
1.77V
ALL INPUT PULSES
90%
10%
90%
10%
3 ns
62148V–3
Switching Characteristics[4] Over the Operating Range
62148V–55
62148V–70
Parameter
Description
Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
WRITE CYCLE[7]
55
70
ns
55
70
ns
10
10
ns
55
70
ns
20
35
ns
5
5
ns
20
25
ns
10
10
ns
20
25
ns
0
0
ns
55
70
ns
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
45
55
ns
tSD
Data Set-Up to Write End
45
55
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[5,6]
0
0
ns
5
5
ns
20
25
ns
Notes
4. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3

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