DM9102A Ver la hoja de datos (PDF) - Unspecified
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DM9102A Datasheet PDF : 77 Pages
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15:14 TSB
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TXSC
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FCM
11:10 LBM
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FDM
8 Reserved
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PAM
6
PM
5 Reserved
4
IAFM
Final
Version: DM9102A-DS-F03
August 28, 2000
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DM9102A
Single Chip Fast Ethernet NIC controller
Threshold Bits
These bits are set together with CR6<22> (chose 10Mb or 100Mb) and will decide
the exact FIFO threshold level. The packet transmission will start after the data level
exceeds the threshold value.
Bit15 Bit14 Threshold(100M) Threshold(10M)
0
0
128
72
0
1
256
96
1
0
512
128
1
1
Reserved
Reserved
Transmit Start/stop Command
When set, transmit process will begin by fetching the transmit descriptor for
available packet data to be transmitted (running state). If the fetched descriptor is
owned by the host, transmit process will enter the suspend state and transmit buffer
unavailable (CR5<2>) is set. Otherwise it will begin to move data from host to
FIFO and transmit out after reaching threshold level.
When reset, transmit process is placed in the stopped state after completing the
transmission of the current frame.
Force Collision Mode
When set, the transmission process is forced to be the collision status. Meaningful
only in the internal loopback mode.
Loopback Mode
These bits decide two loopback modes besides normal operation. External
loopback mode expects transmitted data back to receive path and makes no
collision detection.
Bit11
0
0
1
1
Bit10
0
1
0
1
Loopback Mode
normal
internal loopback
internal PHY digital loopback
internal PHY analog loopback
Full-duplex Mode
This bit is set to make DM9102A operate in the full-duplex mode. Transmit and
receive processes can work simultaneously.
There is no collision detection needed during this mode operation.
Must be zero.
Pass All Multicast
When set, any packet with a multicast destination address is received by the
DM9102A. The packet with a physical address will also be filtered based on the
filter mode setting.
Promiscuous mode
When set, any incoming valid frame is received by the DM9102A, and no matter
what the destination address. The DM9102A is initialized to this mode after reset
operation.
Must be Zero.
Inverse Address Filtering Mode
It is set to indicate the DM9102A operate in a Inverse Filtering Mode. This is a read
only bit and mapped from the setup frame together with CR6<2>, CR6<0> setting.
That is, it is valid only during perfect filtering mode.
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