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DM9102A

Single Chip Fast Ethernet NIC controller

Unspecified 

DM9102A

Single Chip Fast Ethernet NIC controller

Expansion ROM Base Address (xxxxxx30 - PCIROM)

31

ROM Base Address

ROM Base Address

18 17

11 10 9

10

00000000000000 0

Reserved

R/W

Bit

31:10

Default

00h

9:1 000000000

0

0

Type

RW

RO

RW

Description

ROM Base Address With 256K Boundary

PCIROM bit17~10 are hardwired to 0, indicating ROM Size is up to 256K Size

Reserved Bits Read As 0

Expansion ROM Decoder Enable/Disable

If this bit and the memory space access bit are both set to 1, the DM9102A will

responds to its expansion ROM.

Capabilities Pointer (xxxxxx34 - Cap _Ptr)

31

Reserved

Capability Pointer

87

0

01 01 0 0 0 0

Bit

Default

31:8 000000h

7:0 01010000

Type

RO

RO

Description

Reserved

Capability Pointer

The Cap_Ptr provides an offset (default is 50h) into the function’s PCI Configuration

Space for the location of the first term in the Capabilities Linked List. The Cap_Ptr

offset is DOUBLE WORD aligned so the two least significant bits are always “0”s

Final

21

Version: DM9102A-DS-F03

August 28, 2000

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