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4S204BIL

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER

Integrated Device Technology 

ICS854S204I

LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ V /2 is

DD

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V

DD

and R2/R1 = 0.609.

VDD

Single Ended Clock Input

R1

1K

PCLK

V_REF

C1

0.1u

nPCLK

R2

1K

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

OUTPUTS:

PCLK/nPCLK INPUTS

For applications not requiring the use of the differential input,

both PCLK and nPCLK can be left floating. Though not required,

but for additional protection, a 1kΩ resistor can be tied from PCLK

to ground.

LVDS OUTPUTS

All unused LVDS output pairs can be either left floating or

terminated with 100Ω across. If they are left floating, there should

be no trace attached.

LVPECL OUTPUTS

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

IDT™ / ICS™ LVDS, LVPECL FANOUT BUFFER

10

ICS854S204BGI REV. A JUNE 4, 2008

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