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4S204BIL Datasheet PDF : 19 Pages
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LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIAL-
TO-LVDS, LVPECL FANOUT BUFFER
ICS854S204I
GENERAL DESCRIPTION
The ICS854S204I is a low skew, high performance
ICS
dual, programmable 1-to-2 Differential-to-LVDS,
HiPerClockS™ LVPECL Fanout Buffer and a member of t h e
HiPerClock S™ family of High Performance Clock
Solutions from IDT. The PCLKx, nPCLKx pairs can
accept most standard differential input levels. With the selection of
SEL_OUT signal, outputs can be selected be to either LVDS or
LVPECL levels. The ICS854S204I is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed out-
put and bank skew characteristics make the ICS854S204I
ideal for those clock distribution applications demanding well
defined performance and repeatability.
FEATURES
Two programmable differential LVDS or LVPECL output banks
Two differential clock input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, SSTL, CML
Maximum output frequency: 3GHz
Translates any single ended input signal to LVDS levels
with resistor bias on nPCLKx inputs
Output skew: 15ps (maximum)
Bank skew: 15ps (maximum)
Propagation delay: 500ps (maximum)
Additive phase jitter, RMS: 0.15ps (typical)
Full 3.3V or 2.5V power supply
POWER SUPPLY CONFIGURATION TABLE
-40°C to 85°C ambient operating temperature
3.3V Operation
2.5V Operation
VDD = 3.3V
VTAP = nc
V = 2.5V
DD
VTAP = 2.5V
Available in lead-free (RoHS 6) package
SEL_OUT FUNCTION TABLE
SEL_OUT
0
1
Output Level
LVDS
LVPECL
BLOCK DIAGRAM
V
TAP
SEL_OUT Pulldown
PCLKA Pulldown
nPCLKA Pullup
PCLKB Pulldown
nPCLKB Pullup
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
PIN ASSIGNMENT
PCLKA 1
nPCLKA 2
QA0 3
nQA0 4
QA1 5
nQA1 6
VTAP 7
GND 8
16 nPCLKB
15 PCLKB
14 QB0
13 nQB0
12 QB1
11 nQB1
10 VDD
9 SEL_OUT
ICS854S204I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
IDT/ ICSLVDS, LVPECL FANOUT BUFFER
1
ICS854S204BGI REV. A JUNE 4, 2008

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