IDT72255L10G Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT72255L10G Datasheet PDF : 30 Pages
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IDT72255/72265 SyncFIFO™
8,192 x 18, 16,384 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
two pointers operate independently; however, a read and a
write should not be performed simultaneously to the offset
registers. A Master Reset initializes both pointers to the
Empty Offset (LSB) register. A Partial Reset has no effect on
the position of these pointers.
Once serial offset loading has been selected, then pro-
gramming PAE and PAF procedes as follows: When LD and
SEN are set LOW, data on the SI input are written, one bit for
each WCLK rising edge, starting with the Empty Offset (13 bits
for the 72255, 14 bits for the 72265), ending with the Full Offset
(13 bits for the 72255, 14 bits for the 72265). A total of 26 bits
are necessary to program the 72255; a total of 28 bits are
necessary to program the 72265. Individual registers cannot
be loaded serially; rather, both must be programmed in
sequence, no padding allowed. PAE and PAF can show a
valid status only after the the full set of bits have been entered.
The registers can be re-programmed, as long as both offsets
are loaded. When LD is LOW and SEN is HIGH, no serial write
to the registers can occur.
Once parallel offset loading has been selected, then
programming PAE and PAF procedes as follows: When LD
and WEN are set LOW, data on the inputs Dn are written into
the Empty Offset Register on the first LOW-to-HIGH transition
of WCLK. Upon the second LOW-to-HIGH transition of
WCLK, data at the inputs are written into the Full Register. The
third transition of WCLK writes, once again, to the Empty
Offset Register.
To ensure proper programming (serial or parallel) of the
offset registers, no read operation is permitted from the time
of reset (master or partial) to the time of programming. (During
this period, the read pointer must be pointing to the first
location of the memory array.) After the programming has
been accomplished, read operations may begin.
Write operations to memory are allowed before and during
the parallel programming sequence. In this case, the pro-
gramming of all offset registers does not have to occur at one
time. One or two offset registers can be written to and then,
by bringing LD HIGH, write operations can be redirected to the
FIFO memory. When LD is set LOW again, and WEN is LOW,
the next offset register in sequence is written to. As an
alternative to holding WEN LOW and toggling LD, parallel
programming can also be interrupted by setting LD LOW and
toggling WEN.
Write operations to memory are allowed before and during
the serial programming sequence. In this case, the program-
ming of all offset bits does not have to occur at once. A select
number of bits can be written to the SI input and then, by
bringing LD and SEN HIGH, data can be written to FIFO
memory via Dn by toggling WEN. When WEN is brought HIGH
with LD and SEN restored to a LOW, the next offset bit in
sequence is written to the registers via SI. If a mere interuption
of serial programming is desired, it is sufficient either to set LD
LOW and deactivate SEN or to set SEN LOW and deactivate
LD. Once LD and SEN are both restored to a LOW level, serial
offset programming continues from where it left off.
Note that the status of a partial flag (PAE or PAF) output is
invalid during the programming process. From the time
parallel programming has begun, a partial flag output will not
be valid until the appropriate offset word has been written to
the register pertaining to that flag. From the time serial
programming has begun, neither partial flag will be valid until
the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves
either of the above criteria; PAF will be valid after two more
rising WCLK edges plus tPAF, PAE will will be valid after the
next two rising RCLK edges plus tPAE (Add one more RCLK
cycle if tSKEW2 is not met.)
The act of reading the offset registers employs a dedicated
read offset register pointer. The contents of the offset registers
can be read on the output lines when LD is set LOW and REN
is set LOW; then, data are read via Qn from the Empty Offset
Register on the first LOW-to-HIGH transition of RCLK. Upon
the second LOW-to-HIGH transition of RCLK, data are read
from the Full Offset Register. The third transition of RCLK,
reads, once again, from the Empty Offset Register.
It is permissable to interrupt the the offset register access
sequence with reads or writes to memory . The interruption is
accomplished by deasserting REN, LD, or both together.
When REN and LD are restored to a LOW level, access of the
registers continues where it left off.
LD functions the same way in both IDT Standard and
FWFT modes.
FREQUENCY SELECT INPUT (FS)
An internal state machine manages the movement of data
through the SuperSync FIFO. The FS line determines whether
RCLK or WCLK will synchronize the state machine. Tie FS to
VCC if the RCLK line is running at a lower frequency than the
WCLK line. In this case, the state machine will be synchro-
nized to WCLK. Tie FS to GND if the RCLK line is running at
a higher frequency than the WCLK line. In this case, the state
machine will be synchronized to RCLK. Note that FS must be
set so the clock line running at the higher frequency drives the
state machine; this ensures efficient handling of the data
within the FIFO. If the same clock signal drives both the WCLK
and the RCLK pins, then tie FS to GND.
The frequency of the clock tied to the state machine
(referred to as the "selected clock") may be changed at any
time, so long as it is always greater than or equal to the
frequency of the clock that is not tied to the state machine
(referred to as the "non-selected clock"). The frequency of the
non-selected clock can also be varied with time, so long as it
never exceeds the frequency of the selected clock. To be
more specific, the frequencies of both RCLK and WCLK may
be varied during FIFO operation, provided that, at any given
point in time, the cycle period of the selected clock is equal to
or less than the cycle period of the non-selected clock.
The selected clock must be continuous. It is, however,
permissible to stop the non-selected clock. Note, so long as
RCLK is idle, EF/OR and PAE will not be updated. Likewise,
as long as WCLK is idle, FF/IR and PAF will not be updated.
Changing the FS setting during FIFO operation (i.e. read-
ing or writing) is not permitted; however, such a change at the
time of Master Reset or Partial Reset is all right. FS is an
asynchronous input.
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