IDT72255L10G Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72255L10G

CMOS SUPERSYNC FIFO 8,192 x 18, 16,384 x 18

Integrated Device Technology 

IDT72255/72265 SyncFIFO™

8,192 x 18, 16,384 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

gramming offset registers may not be convenient.

The Retransmit function allows the read pointer to be reset

to the first location in the RAM array. It is synchronized to

RCLK when RT is LOW. This feature is convenient for

sending the same data more than once.

If, at any time, the FIFO is not actively performing a function,

the chip will automatically power down. This occurs if neither

a read nor a write occurs within 10 cycles of the faster clock,

RCLK or WCLK. During the Power Down state, supply current

consumption (ICC2) is at a minimum. Initiating any operation

(by activating control inputs) will immediately take the device

out of the Power Down state.

The IDT72255/72265 are depth expandable. The addition

of external components is unnecessary. The IR and OR

functions, together with REN and WEN, are used to extend the

total FIFO memory capacity.

The FS line ensures optimal data flow through the FIFO. It

is tied to GND if the RCLK frequency is higher than the WCLK

frequency or to Vcc if the RCLK frequency is lower than the

WCLK frequency

The IDT72255/72265 is fabricated using IDT’s high speed

submicron CMOS technology.

PIN CONFIGURATIONS (CONT.)

11

DNC Q5 VCC Q2 Q1 GND D1 D3 D5

10 Q6 GND Q4 Q3 GND Q0 D0 D2 D4 D6 D7

09 Q8 Q7

D9 D8

08 Q10 Q9

D11 D10

07 Q11 GND

D13 D12

06 Q13 Q12

D15 D14

05 Q14 VCC

04 GND Q15

Pin 1 Designator

D17 D16

VCC GND

03 Q17 Q16

SEN FS

02 DNC OE

REN GND PAE

HF

FF/

IR

DNC

LD

WCLK WEN

01

RT

RCLK

EF/

OR

VCC

PAF

GND

FWFT/

SI

MRS

PRS

A B C D E F GH J K L

3037 drw 03

PGA (G68-1, order code: G)

TOP VIEW

NOTES:

1. DNC = Do not connect

3

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