M38B59MD-XXXFS Ver la hoja de datos (PDF) - Renesas Electronics
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M38B59MD-XXXFS Datasheet PDF : 70 Pages
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 16 Timing Requirements (VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
____________
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SIN)
th(SCLK–SIN)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “H” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input set up time
Serial I/O input hold time
Min.
2.0
238
60
60
20
5.0
5.0
4.0
1.6
1.6
80
80
0.95
400
400
200
200
Limits
Typ.
SWITCHING CHARACTERISTICS
Table 17 Switching Characteristics (VCC = 4.0 to 5.5V, VSS = 0V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
tWH(SCLK)
Parameter
Serial I/O clock output “H” pulse width
Test conditions
CL = 100 pF
Limits
Min.
Typ.
tC(SCLK)/2–160
tWL(SCLK)
td(SCLK–SOUT)
tv(SCLK–SOUT)
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output valid time
CL = 100 pF
tC(SCLK)/2–160
0
tr(SCLK)
Serial I/O clock output rising time
CL = 100 pF
tf(SCLK)
Serial I/O clock output falling time
CL = 100 pF
tr(Pch–strg)
P-channel high-breakdown voltage
CL = 100 pF
55
output rising time (Note 1)
VEE = VCC–43 V
tr(Pch–weak)
P-channel high-breakdown voltage
CL = 100 pF
1.8
output rising time (Note 2)
VEE = VCC–43 V
Notes 1: When bit 7 of the FLDC mode register (address 0EF416) is at “0”.
2: When bit 7 of the FLDC mode register (address 0EF416) is at “1”.
Unit
Max.
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
Unit
Max.
ns
ns
0.2 tc
ns
ns
40
ns
40
ns
ns
µs
Serial I/O clock
P52/SCLK11,
P53/SCLK12,
output port
P56/SCLK21,
P57/SCLK22
CL
Fig. 73 Circuit for Measuring Output Switching Characteristics
High-breakdown
P-channel open-
drain output port
(Note)
P0,P1,P2,
P3,P80–P83
CL
VEE
Note: Ports P2 and P8 need external resistors.
66
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