MAX3940E_D Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Lista de partido
MAX3940E_D Datasheet PDF : 13 Pages
| |||
10Gbps EAM Driver with Integrated
Bias Network
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -5.5V to -4.9V, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, and TA = +25°C, unless
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Modulation Set Bandwidth
Modulation depth 10%, 50Ω driver load,
see Figure 2
5
MHz
MODSET Input Resistance
20
kΩ
Modulation-Current Temperature
Stability
(Note 6)
-480
+480 ppm/°C
Modulation-Current Setting Error
50Ω driver load, TA = +25°C
-5
+5
%
Output Resistance
ROUT OUT to GND
42.5
50
58.5
Ω
Total Off Current
BIASSET = VEE, MODEN = VEE, MODSET =
VEE, DATA+ = high, DATA- = low
1
mA
Output Return Loss
Output Edge Speed
Setup/Hold Time
Pulse-Width Adjustment Range
RLOUT
tSU, tHD
IBIAS = 30mA,
IMOD = 50mA
≤ 5GHz
20% to 80% (Notes 6, 8)
Figure 3 (Note 6)
(Notes 6, 8)
8
dB
23
32
ps
25
ps
±20 ±50
ps
Pulse-Width Control Input Range
(Single Ended)
For PWC+ and PWC-
VEE +
0.5
VEE +
1.5
V
Pulse-Width Control Input Range
(Differential)
Output Overshoot
Driver Random Jitter
Driver Deterministic Jitter
CONTROL INPUTS
Input High Voltage
δ
RJDR
DJDR
VIH
(PWC+) - (PWC-)
(Notes 6, 8)
(Note 6)
PWC- = GND (Notes 6, 9)
(Note 10)
-0.5
+0.5
V
-10
+10
%
0.3
1.1 psRMS
6.8
14
psP-P
VEE +
V
2.0
Input Low Voltage
Input Current
VIL
(Note 10)
(Note 10)
VEE +
V
0.8
-80
+80
µA
Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply
current after the retiming function has been disabled.
Note 2: Power-supply noise rejection is specified as PSNR = 20Log(Vnoise (on Vcc) / ∆VOUT). VOUT is the voltage across a 50Ω load.
Vnoise (on Vcc) = 100mVP-P.
Note 3: For DATA+, DATA-, CLK+, and CLK-.
Note 4: CLK input characterized at 10.7Gbps
Note 5: RBSEQV = (VBIASSET - VEE) / IOUT with MODEN = VEE, DATA+ = high, and DATA- = low.
Note 6: Guaranteed by design and characterization using the circuit shown in Figure 4.
Note 7: RMODEQV = (VMODSET - VEE) / (IOUT - 37mA) with BIASSET = VEE.
Note 8: 50Ω load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern.
Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter).
Measured with a 10.7Gbps 27 - 1 PRBS pattern with eighty 0s and eighty 1s inserted in the data pattern.
Note 10: For MODEN and PLRT.
_______________________________________________________________________________________ 3
Share Link: 