MT8920B-1 Ver la hoja de datos (PDF) - Mitel Networks
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MT8920B-1 Datasheet PDF : 29 Pages
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CMOS MT8920B
ADDRESS BITS
A6 A5 A4 A3 A2 A1
000000
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
001111
X10000
X10000
X10001
X10010
X10010
X10011
X10011
X10100
X10100
X10101
X10101
X10110
X10110
100000
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
101111
NOTES: X is don’t care
A6 is bit D4 of Control Register 1
REGISTERS
A0
READ
0
Rx0 - Channel 0
•
•
•
•
•
•
1
Rx0 - Channel 31
0
Control Register 1
1
Control Register 2
0
Interrupt Vector Register
0
Interrupt Flag Register 1
1
Interrupt Flag Register 2
0
Image Register 1
1
Image Register 2
0
Interrupt Mask Register 1
1
Interrupt Mask Register 2
0
Match Byte Register 1
1
Match Byte Register 2
0 Interrupt Channel Address 1
1 Interrupt Channel Address 2
0
Rx0 - Channel 0
•
•
•
•
•
•
1
Rx0 - Channel 31
Table 2. Mode 1 Address Map
WRITE
Tx0 - Channel 0
•
•
•
Tx0 - Channel 31
Control Register 1
Control Register 2
Interrupt Vector Register
-
-
-
-
Interrupt Mask Register 1
Interrupt Mask Register 2
Match Byte Register 1
Match Byte Register 2
Interrupt Channel Address 1
Interrupt Channel Address 2
Tx1 - Channel 0
•
•
•
Tx1 - Channel 31
Bit
Name
Description
7
(Unused)
6
IRQRST Interrupt Reset. This bit, when set high, automatically clears the Interrupt Flag Register
and the Interrupt Image Register without these registers being serviced. This bit
automatically resets to zero after the register clear is completed.
5
RAMCON RAM Configuration. This bit configures Tx0, Tx1 and Rx0 RAMS for 32 or 24 byte
operation. D5 = 0 for 32 channel; D5 = 1 for 24 channel.
4
A6
Address Bit A6. This bit extends the addressing range for access to Tx1 memory.
3 IRQ2MODE Interrupt Source 2 Mode Select. This bit configures the source 2 interrupt generator.
D3 = 0 selects “static” interrupt mode; D3 = 1 selects “dynamic” interrupt mode.
2 IRQ1MODE Interrupt Source 1 Mode Select. This bit configures the source 1 interrupt generator.
D2 = 0 selects “static” interrupt mode; D2 = 1 selects “dynamic” interrupt mode.
1
IRQ2EN Interrupt Source 2 Enable. IRQ2EN = 1 enables interrupts to occur from source 2.
0
IRQ1EN Interrupt Source 1 Enable. IRQ1EN = 1 enables interrupts to occur from source 1.
Table 3. Control Register 1 Bit Definitions
3-9
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