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PIC18F6520

64/80-Pin High-Performance, 256 Kbit to 1 MbitEnhanced Flash Microcontrollers with A/D

Microchip Technology 

PIC18F6520/8520/6620/8620/6720/8720

TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Pin

PIC18F6X20 PIC18F8X20 Type

Buffer

Type

Description

PORTG is a bidirectional I/O port.

RG0/CCP3

RG0

CCP3

3

5

I/O

ST

Digital I/O.

I/O

ST

Capture3 input/Compare3 output/

PWM3 output.

RG1/TX2/CK2

RG1

TX2

CK2

4

6

I/O

ST

Digital I/O.

O

—

USART 2 asynchronous transmit.

I/O

ST

USART 2 synchronous clock

(see RX2/DT2).

RG2/RX2/DT2

RG2

RX2

DT2

5

7

I/O

ST

Digital I/O.

I

ST

USART 2 asynchronous receive.

I/O

ST

USART 2 synchronous data

(see TX2/CK2).

RG3/CCP4

RG3

CCP4

RG4/CCP5

RG4

CCP5

6

8

I/O

ST

Digital I/O.

I/O

ST

Capture4 input/Compare4 output/

PWM4 output.

8

10

I/O

ST

Digital I/O.

I/O

ST

Capture5 input/Compare5 output/

PWM5 output.

Legend:

Note 1:

2:

3:

4:

5:

6:

TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

I = Input

P = Power

CMOS = CMOS compatible input or output

Analog = Analog input

O

= Output

OD = Open-Drain (no P diode to VDD)

Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except

Microcontroller).

Default assignment when CCP2MX is set.

External memory interface functions are only available on PIC18F8X20 devices.

CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.

AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for

proper operation of the part in user or ICSP modes. See parameter D001A for details.

DS39609C-page 18

 2003-2013 Microchip Technology Inc.

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