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RTL8201CP-LF

SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto Crossover)

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RTL8201CP

Datasheet

7. Functional Description

The RTL8201CP PHYceiver is a physical layer device that integrates 10Base-T and

100Base-TX/100Base-FX functions, and some extra power management features into a 48-pin single chip

that is used in 10/100 Fast Ethernet applications. This device supports the following functions:

• MII interface with MDC/MDIO SMI management interface to communicate with MAC

• IEEE 802.3u clause 28 Auto-Negotiation ability

• Flow control ability support to cooperate with MAC

• Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO

• Flexible LED configuration

• 7-wire SNI (Serial Network Interface) support (only in 10Mbps mode)

• Power Down mode support

• 4B/5B transform

• Scrambling/De-scrambling

• NRZ to NRZI, NRZI to MLT-3

• Manchester Encode and Decode for 10Base-T operation

• Clock and Data recovery

• Adaptive Equalization

• Far End Fault Indication (FEFI) in fiber mode

7.1. MII and Management Interface

7.1.1. Data Transition

To set the RTL8201CP for MII mode operation, pull the MII/SNIB pin high and set the ANE, SPEED,

and DUPLEX pins.

The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying

a standard interface between the PHY and MAC layer. This interface operates at two frequencies –

25MHz and 2.5MHz to support 100Mbps/10Mbps bandwidth for both transmit and receive functions.

Transmission

The MAC asserts the TXEN signal. It then changes byte data into 4-bit nibbles and passes them to the

PHY via TXD[0..3]. The PHY will sample TXD[0..3] synchronously with TXC — the transmit clock

signal supplied by PHY – during the interval TXEN is asserted.

Reception

The PHY asserts the RXEN signal. It passes the received nibble data RXD[0..3] clocked by RXC. CRS

and COL signals are used for collision detection and handling.

In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is

recognized as IDLE it will be de-asserted. In 10Base-T mode, CRS will assert when the 10M preamble

has been confirmed and will be de-asserted when the IDLE pattern has been confirmed.

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

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Track ID: JATR-1076-21 Rev. 1.21

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