RTL8305SC-LF Ver la hoja de datos (PDF) - Unspecified

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RTL8305SC-LF

SINGLE-CHIP 5-PORT 10/100MBPS SWITCH CONTROLLER WITH DUAL MII INTERFACES

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RTL8305SC

Datasheet

FIGURE 1. BLOCK DIAGRAM .........................................................................................................................................................6

FIGURE 2. PIN ASSIGNMENTS ........................................................................................................................................................7

FIGURE 3. PORT 4 OPERATING MODE OVERVIEW........................................................................................................................93

FIGURE 4. TRADITIONAL APPLICATION........................................................................................................................................99

FIGURE 5. DUAL MII APPLICATION DIAGRAM ..........................................................................................................................100

FIGURE 6. DUAL MII MODE WITH 1 MII-MAC + 1 MII-PHY (100BASE-T UTP) INTERFACES APPLICATION CIRCUIT............101

FIGURE 7. DUAL MII MODE WITH 1 MII-MAC + 1 MII-PHY (100BASE-FX MODE) INTERFACES APPLICATION CIRCUIT.......101

FIGURE 8. DUAL MII MODE WITH 1 MII-PHY + 1 MII-PHY (100BASE-T UTP) INTERFACES APPLICATION CIRCUIT .............102

FIGURE 9. DUAL MII MODE WITH 1 SNI-PHY + 1 MII-PHY (100BASE-T UTP) INTERFACES APPLICATION CIRCUIT.............102

FIGURE 10. RESET.......................................................................................................................................................................115

FIGURE 11. START AND STOP DEFINITION ...................................................................................................................................117

FIGURE 12. OUTPUT ACKNOWLEDGE ..........................................................................................................................................117

FIGURE 13. RANDOM READ ........................................................................................................................................................118

FIGURE 14. SEQUENTIAL READ ...................................................................................................................................................118

FIGURE 15. VLAN GROUPING EXAMPLE....................................................................................................................................120

FIGURE 16. TAGGED AND UNTAGGED PACKET FORWARDING WHEN 802.1Q TAG AWARE VLAN IS DISABLED ...........................122

FIGURE 17. INPUT DROP VS. OUTPUT DROP ................................................................................................................................126

FIGURE 18. LOOP EXAMPLE ........................................................................................................................................................127

FIGURE 19. PORT 4 LOOPBACK ...................................................................................................................................................128

FIGURE 20. REG. 0.14 LOOPBACK ...............................................................................................................................................129

FIGURE 21. FLOATING AND PULL-DOWN OF LED PINS ...............................................................................................................130

FIGURE 22. TWO PIN BI-COLOR LED FOR SPD FLOATING OR PULL-HIGH ..................................................................................131

FIGURE 23. TWO PIN BI-COLOR LED FOR SPD PULL-DOWN ......................................................................................................131

FIGURE 24. USING A PNP TRANSISTOR TO TRANSFORM 3.3V INTO 1.8V....................................................................................132

FIGURE 25. RECEPTION DATA TIMING OF MII/SNI/SMI INTERFACE ...........................................................................................136

FIGURE 26. TRANSMISSION DATA TIMING OF MII/SNI/SMI INTERFACE .....................................................................................136

FIGURE 27. UTP APPLICATION FOR TRANSFORMER WITH CONNECTED CENTRAL TAP................................................................141

FIGURE 28. UTP APPLICATION FOR TRANSFORMER WITH SEPARATE CENTRAL TAP....................................................................142

FIGURE 29. 100BASE-FX WITH 3.3V FIBER TRANSCEIVER APPLICATION ...................................................................................143

FIGURE 30. 100BASE-FX WITH 5V FIBER TRANSCEIVER APPLICATION ......................................................................................144

5-port 10/100Mbps Single-Chip Dual MII Switch Controller xii

Track ID: JATR-1076-21 Rev. 1.2

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