SC18IM700(2007) Ver la hoja de datos (PDF) - NXP Semiconductors.

Número de pieza

componentes Descripción

Lista de partido

SC18IM700
(Rev.:2007)

Master I2C-bus controller with UART interface

NXP Semiconductors. 

NXP Semiconductors

SC18IM700

Master I2C-bus controller with UART interface

2 SYSTEM

CLOCK

CYCLES

VDD

P

P very P

strong

weak

weak

pin latch data

VSS

input data

Fig 13. Quasi-bidirectional output configuration

GPIOn

glitch rejection

002aac076

9.2.2.2 Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt triggered input that

also has a glitch suppression circuit.

input data

Fig 14. Input-only configuration

GPIO pin

glitch rejection

002aab884

9.2.2.3 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a port output. A push-pull port pin has a Schmitt

triggered input that also has a glitch suppression circuit.

VDD

P

strong

pin latch data

input data

Fig 15. Push-pull output configuration

N

VSS

GPIO pin

glitch rejection

002aab885

SC18IM700_2

Product data sheet

Rev. 02 — 10 August 2007

© NXP B.V. 2007. All rights reserved.

11 of 22

Share Link: