SC18IM700(2007) Ver la hoja de datos (PDF) - NXP Semiconductors.
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SC18IM700 Datasheet PDF : 22 Pages
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NXP Semiconductors
SC18IM700
Master I2C-bus controller with UART interface
Table 7. I2C-bus clock frequency
I2CClk
(I2CClkH + I2CClkL)
I2C-bus clock frequency
10 (minimum)
369 kHz
15
246 kHz
25
147 kHz
30
123 kHz
50
74 kHz
60
61 kHz
100
37 kHz
Remark: The numbers used in the formulas are in decimal, but the numbers to program
I2CClkH and I2CClkL are in hex.
9.2.6 I2C-bus time-out (I2CTO)
The time-out register is used to determine the maximum time that SCL is allowed to be
LOW before the I2C-bus state machine is reset.
When the I2C-bus interface is running, I2CTO is loaded after each I2C-bus state transition.
Table 8.
Bit
7:1
0
I2CTO - I2C-bus time-out register (address 0x09h) bit description
Symbol
Description
TO[7:1]
time-out value
TE
enable/disable time-out function
logic 0 = disable
logic 1 = enable
The least significant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1
will enable the time-out function. The time-out period can be calculated as follows:
time-out period = -I--2----C----T----O--5--[-7--7-6--:-0-1--0--]---×-----2---5---6- seconds
The time-out value may vary, and it is an approximate value.
9.2.7 I2C-bus status register (I2CStat)
This register reports the I2C-bus transmit and receive frame status, whether the frame
transmits correctly or not.
Table 9. I2C-bus status
Bit 7 Bit 6 Bit 5 Bit 4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 3
0
0
0
1
Bit 2
0
0
0
0
Bit 1
0
0
1
0
Bit 0
0
1
0
0
I2C-bus status description
I2C_OK
I2C_NACK_ON_ADDRESS
I2C_NACK_ON_DATA
I2C_TIME_OUT
SC18IM700_2
Product data sheet
Rev. 02 — 10 August 2007
© NXP B.V. 2007. All rights reserved.
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