NXP Semiconductors
SC18IS600/601
SPI to I2C-bus interface
SS
tSPIF
tSPILEAD
tSPIF
TCLCL
tSPIR
tSPICLKL tSPICLKH
SPICLK
(input)
MISO
(output)
tSPIOH
tSPIDV
tSPIA
not defined
tSPIOH
tSPIDV
slave MSB/LSB out
tSPIDSU tSPIDH
MOSI
(input)
MSB/LSB in
Fig 21. SPI slave timing (Mode 3)
tSPILAG
tSPIR
tSPIOH
tSPIDV
tSPIDSU
tSPIDIS
slave LSB/MSB out
tSPIDSU tSPIDH
LSB/MSB in
002aab797
VDD − 0.5 V
0.45 V
Fig 22. External clock timing
0.2VDD + 0.9 V
0.2VDD − 0.1 V
tCHCL
tCLCX
tCHCX
tCLCH
TCLCL
002aab886
SC18IS600_601_3
Product data sheet
Rev. 03 — 13 December 2006
© NXP B.V. 2006. All rights reserved.
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