CS5513-BS(2000) Ver la hoja de datos (PDF) - Cirrus Logic
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CS5513-BS Datasheet PDF : 26 Pages
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CS5510/11/12/13
16 and 20-Bit, 8-Pin ∆Σ ADC
Features
l Delta-Sigma Analog-to-Digital Converter
– Linearity Error: 0.0015% FS
– Noise Free Resolution: Up to 17-Bits
l Differential Bipolar Analog Inputs
l VREF Input Range from 250 mV to 5 V
l 50/60 Hz Simultaneous Rejection
(CS5510/12)
l 16 to 326 Hz Output Word Rate
l On-Chip Oscillator (CS5511/13)
l Power Supply Configurations:
– V+ = 5 V, V- = 0 V
– Multiple Dual Supply Arrangements
l Low Power Consumption
– Normal Mode, 2.5 mW
– Sleep Mode, 10 µW
l Low-Cost, Compact, 8-Pin Package
General Description
The CS5510/11/12/13 are low-cost, easy-to-use, ∆Σ An-
alog-to-Digital Converters (ADCs) which use charge
balance techniques to achieve 16-bit (CS5510/11) and
20-bit (CS5512/13) performance. The ADCs are avail-
able in a space efficient 8-pin SOIC package and are
optimized for measuring signals in weigh scale, process
control, and other industrial applications.
To accommodate these applications, the ADCs include
a fourth order ∆Σ modulator and a digital filter. When
configured with an external master clock of 32.768 kHz,
the filter in the CS5510/12 provides better than 80 dB of
simultaneous 50 and 60 Hz line rejection, and outputs
conversion words at 53.5 Hz. The CS5511/13 include an
on-chip oscillator which eliminates the need for an exter-
nal clock source.
Low power, a flexible supply, a compact pinout, and
ease of use make these products ideal solutions for cost
conscience and space constrained applications.
ORDERING INFORMATION
See page 23.
AIN+
AIN-
VREF
V+
1X
Differential
CS
4th Order
Digital Filter
Delta-Sigma
Output
1X
Modulator
Control
Logic
SDO
SCLK
Oscillator
(CS5511/13 only)
Clock
Gen.
(CS5510/12 only)
V-
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2000
(All Rights Reserved)
JUN ‘00
DS337F1
1
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