UPD4990AC Ver la hoja de datos (PDF) - NEC => Renesas Technology

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UPD4990AC

SERIAL I/O CALENDAR & CLOCK CMOS LSI

NEC => Renesas Technology 

µPD4990A

• Command input

(1) 3-bit binary code input: C2, C1, C0

(2) 4-bit serial transfer command input: C3', C2', C1', C0'

• Number of commands

Register control

TP select

TP control

Test mode set

C2, C1, C0

4

3

0

1

C'3, C'2, C'1, C'0

4

8

3

1

• Commands (C3', C2', C1', C0' commands are made effective only when [C2, C1, C0] = [1, 1, 1].)

(1) Register control

[C2, C1, C0] / [C3', C2', C1', C0']

° Register Hold Mode

[C2, C1, C0]

[0, 0, 0] / [0, 0, 0, 0]

The 40-bit shift register is held. The year function is ineffective.

[C3', C2', C1', C0']

The 48-bit shift register is held.

The command register is not held.

* The DATA OUT output frequency is 1 Hz.

° Register Shift Mode

[C2, C1, C0]

[0, 0, 1] / [0, 0, 0, 1]

The 40-bit shift register data can be shifted. The year function is ineffective.

[C3', C2', C1', C0']

Data in 52-bit shift registers (including command registers) can be shifted. For command register, data can

be always shifted using the serial command transfer mode.

* The DATA OUT output is LSB data from the shift register.

° Time Set and Counter Hold Mode

[C2, C1, C0]

[0, 1, 0] / [0, 0, 1, 0]

Data is transferred from the 40-bit shift register to the time counter. The year function is ineffective.

[C3', C2', C1', C0']

Data is transferred from the 48-bit shift register to the time counter.

* This command is used to reset the last 10-15 of 15 Stage Binary Divider and holds the time counter.

15 Stage Binary Divider resetting and time counter release are executed by the following:

[C2, C1, C0] = [0, 0, 0] [0, 0, 1] [0, 1, 1] [C3', C2', C1', C0'] = [0, 0, 0, 0] [0, 0, 0, 1] [0, 0, 1, 1]

The time setting accuracy is ±15.625 ms.

The DATA OUT pin outputs LSB data (0 or 1) from the shift register.

After this command is executed, the 40-/48-bit shift register is held and data cannot be shifted.

° Time Read Mode

[C2, C1, C0]

[0, 1, 1] / [0, 0, 1, 1]

Data is transferred from the time-counter to the 40-bit shift register. The year function is ineffective.

[C3', C2', C1', C0']

Data is transferred from the time counter to the 48-bit shift register.

* The DATA OUT pin output is a 1 Hz frequency.

After this command is executed, the 40-/48-bit shift register is held and data cannot be shifted.

7

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