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TQ8025

2.5 Gigabit/sec 16x16 Digital Crosspoint Switch

TriQuint Semiconductor 

Table 10. TQ8025 Pin Descriptions

TQ8025

PRELIMINARY DATA SHEET

Signal

DI00P-DI15P

DI0N-DI15N

DO0P-DO15P,

DO0N-DO15N

AD00:15

RADD0:1

ADDREN

CLOCK

AUTOCONFIG

READY

LOAD

CONFIGURE

LDMODE

SAD0:3

DAD0:3

VCC, GND, VTT

RESET–

Name/Level

Data input true and complement

Differential CML/PECL input

Data output true and complement

Differential CML/PECL output

Input address; TTL input

RAM address; TTL output, tristate

Enable RADD0:2; TTL input

Clock; TTL input

Configure mode; TTL input

READY; open-drain output

LOAD; TTL input

CONFIGURE; TTL input

Load Mode; TTL input

Source Address; TTL inputs

Destination Address; TTL input

+5V, Ground;

Termination Voltage

Reset; TTL Input

Description

Differential data input ports. VH = 0 V, VL = –300 mV max.

Internal 50-ohm terminations to VTT (CML = 0 V;ECL = –2.0 V).

Differential data output ports. 600 mV min. differential swing.

Serial input address, LSB first in time; ADn programs output port n.

Used to generate address 0-3 during configure load from RAM.

When low, enables RADD0:1; when high, forces RADD0:1 tristate.

Controls cycle time of address generator and AUTOCONFIG.

When high, internal CONFIGURE is automatically generated.

Indicates end of AUTOCONFIG or end of address LOAD cycle

when high. Reset low by RESET-, CONFIG low, or LOAD rising.

Requires external pullup to VCC.

For LDMODE=1, ADDREN=0: AUTOCONFIG=0, rising LOAD causes

ADDR0:1 to generate RAM addresses, then READY is asserted

after four clock ticks. For AUTOCONFIG=1, LOAD rising causes

ADDR0:1 to generate addresses, causing an internal CONFIG

to be generated, after which READY is asserted. For LDMODE=0,

see SAD0:3 and DAD0:3.

Used to load address contents of internal address registers.

Active LOW. Crosspoint will be configured within 4 ns

(objective) of CONFIG falling low.

When floated high, AD0-15 are used for configuration.

When tied low, SAD0-3 and DAD0-3 are used for configuration.

When AUTOCONFIG is disabled, and AD08-15 are ignored.

When LDMODE is low, specifies input address to be connected

to output port specified by DAD0:3. Latched by falling LOAD

(LDMODE=0).

When LDMODE is low, specifies output address to be connected

to input port specified by SAD0:3. Latched by falling LOAD

(LDMODE=0).

Power and ground pins.

VTT = GND for CML inputs; VTT = VCC – 2V for PECL inputs.

While low, programs all output ports to connect to input port 0.

Strobing CONFIG after reset restores user port programming

if device power was stable since last user programming and

during RESET–. Active low, Schmitt triggered.

For additional information and latest specifications, see our website: www.triquint.com

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