KM681000BL Ver la hoja de datos (PDF) - Samsung
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KM681000BL Datasheet PDF : 11 Pages
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KM681000B Family
TIMING WAVEFORM OF WRITE CYCLE (2()CS2 Controlled)
PRELIMINARY
CMOS SRAM
Address
CS1
CS2
WE
Data in
tAS(3)
tWC
tCW(2)
tWR2(4)
tAW
tCW(2)
tWP(1)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of low CS1, high CS2 and low WE. A write begins at the latest transition among CS1 going low, CS2 going high and WE
going low. A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the beginning or write
to the end of write.
2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address calid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at CS1, or WE going high, tWR2 applied in case a write
ends at CS2 going to low.
FUNCTIONAL DESCRIPTION
CS1
CS2
WE
OE
H
X
X
X
X
L
X
X
L
H
H
H
L
H
H
L
L
H
L
X
* X means don't care
Mode
Power Down
Power Down
Output Disable
Read
Write
I/O Pin
High-Z
High-Z
High-Z
Dout
Din
Current Mode
ISB,ISB1
ISB,ISB1
ICC
ICC
ICC
Revision 0.3
April 1996
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