ML6554CU Ver la hoja de datos (PDF) - Fairchild Semiconductor
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ML6554CU Datasheet PDF : 14 Pages
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PRODUCT SPECIFICATION
Applications
Using the ML6554 for SSTL Bus Termination
The circuit schematic in Figure 2 shows a recommended
approach for constructing a bus terminating solution for an
SSTL-2 bus. This circuit can be used in PC memory and
Graphics memory applications as shown in Figures 4 and 5.
Note that the ML6554 can provide the voltage reference
(VREF) and terminating voltages (VTT). Using the layout
as shown in Figures 6, 7, and 8, and measuring the VTT
performance using the test setup as described in Figure 9,
the ML6554 delivered a VTT ± 20mV for 1A to 3A loads
(see Figure 10). Table 1 provides a recommended parts list
for the circuit in Figure 2.
ML6554
Power Handling Capability of the PSOP
Package
Using the board layout shown in Figures 6, 7, and 8; solder-
ing the ML6554 to the board at zero LFPM the temperature
around the package measured 55ºC for 3A loads. Note that a
1 ounce copper plane was used in the board construction.
Airflow is not likely to be needed in the operation of this
device (assuming a board layout similar to that described
above). The power handling performance of the PSOP
package is shown by a study of the package manufacturer for
various airflow vs. θJA conditions in Figure 11.
Bus Termination Solutions for Others Buses
Table 3 provides a summary of various bus termination VREF
& VTT requirements. The ML6554 can be used for those
applications.
TPI
VTT
TO SDRAMS
GND
R1 100Ω
R2 100Ω
C9 0.1µF
C8 0.1µF
C1
820µF
F2V
OS-CON
L1 3.3µH C3 0.1µF
C2
0.1µF
C4 0.1µF
U1
ML6554
1
VDD
2
PVDD1
3
VL1
4
PGND1
5 PGND2
6
VL2
7
PVDD2
8
DGND
16
AVCC
15
VCCQ
14
VREFOUT
13
AGND
12
SHDN
11
VREFIN
10
VFB
9
VDD
R4 100kΩ
R5 1kΩ
C7 1nF
R3
100kΩ
2.5V TO 4V
C5
C6
330µF 330µF
VCCQ
VREFOUT
SHDN
VREFIN
GND
Figure 2.
REV. 1.1.3 3/8/02
5
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