° Oscillator Timing
SED1330
VDD
CLO
YDIS
EXT 0O
tOSP
Power ON
Sleep period
tRCL
tOSS
tFCL
tWL
tWH
tCL
Signal
CLO
EXT φ0
Parameter
Symbol
Time to stable CLO output
after power-ON
tOSP
Time to stable CLO after
sleep OFF
tOSS
External clock rise time
tRCL
External clock fall time
tFCL
External clock high-pulse width tWH
External clock low-pulse width
tWL
External clock cycle
tCL
*1. (tC – tRCL – tFCL) × 475/1000 < tWH, tWL
*2. (tC – tRCL – tFCL) × 525/1000 > tWH, tWL
Rating
Min
Max
—
3
—
1
—
15
—
15
*1
*2
*1
*2
100
—
Unit
Remark
ms
RES = H
20 pF
ms
ns
ns
ns
ns
ns
135