SED1330 Ver la hoja de datos (PDF) - Unspecified

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SED1330

CMOS GRAPHIC LCD CONTROLLER

Unspecified 

SED1330

° Display Memory WRITE Timing

EXTφO

VCE

VA0~VA15

VR/W

VD0~VD7

tC

tW

tASC

tAS tWSC

tOSC

tCE

tAHC

tCYW

tWHC

tOHC

tCA

tAH2

tOH2

Signal

EXT φ0

VCE

VA0 to VA15

VR/W

VD0 to VD7

Parameter

Clock cycle

VCE HIGH-level pulse width

VCE LOW-level pulse width

Write cycle time

VCE address hold time (fall)

VCE address setup time (fall)

VCE address hold time (rise)

VR/W address setup time (fall)

VR/W address hold time (rise)

VCE write setup time (fall)

VCE write hold time (fall)

VCE data input setup time (fall)

VCE data input hold time (fall)

VR/W data hold time (rise)

Symbol

tC

tW

tCE

tCYW

tAHC

tASC

tCA

tAS

tAH2

tWSC

tWHC

tDSC

tDHC

tDH2

Rating

Min

Max

100

—

tC – 40

—

2tC – 40 —

3tC

—

2tC – 40 —

tC – 55

—

5

—

0

—

15

—

tC – 55

—

2tC – 40 —

tWSC – 10 —

2tC – 30 —

10*

50

* Lines VD0 to VD7 are latched.

Unit

Remark

ns

ns

ns

ns

ns

ns

ns CL = 100 pF

ns

+ 1TTL

ns

ns

ns

ns

ns

ns

132

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