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UPD72850A

IEEE1394 400Mbps PHY

NEC => Renesas Technology 

µPD72850A

2. PHY REGISTERS

2.1 Complete Structure for PHY Registers

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Figure 2-1. Complete Structure of PHY Registers

0

1

RHB

IBR

Extended (7)

Max_speed

Link_active Contender

Resume_int

ISBR

Page_select

2

3

4

5

6

Physical_ID

R

Gap_count

Reserved

Total_ports

Reserved

Delay

Jitter

Pwr_class

Loop

Pwr_fail

Timeout Port_event Enab_accel

Reserved

Reserved

Port_select

Register0 (page_select)

Register1 (page_select)

Register2 (page_select)

Register3 (page_select)

Register4 (page_select)

Register5 (page_select)

Register6 (page_select)

Register7 (page_select)

7

PS

Enab_multi

10

Data Sheet S14452EJ1V0DS00

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