UPD72850A Ver la hoja de datos (PDF) - NEC => Renesas Technology
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UPD72850A Datasheet PDF : 48 Pages
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µPD72850A
Field
Physical_ID
R
PS
RHB
IBR
Gap_count
Extended
Total_ports
Max_speed
Delay
Link_active
Contender
Jitter
Table 2-1. Bit Field Description (1/2)
Size R/W Reset value
Description
6
R
000000 Physical_ID value selected from Self_ID period.
1
R
0
If this bit is 1, the node is root.
1: Root
0: Not root
1
R
Cable power status.
1: Cable power on
0: Cable power off
1 R/W
0
Root Hold -off bit. If 1, becomes root at the bus reset.
1 R/W
0
Initiate bus reset.
Setting to 1 begins a long bus reset.
Long bus reset signal duration: 166 µsec.
Returns to 0 at the beginning of bus reset.
6 R/W
111111 Gap count value.
It is updated by the changes of transmitting and receiving the PHY
configuration packet Tx/Rx.
The value is maintained after first bus reset.
After the second bus reset it returns to reset value.
3
R
111
Shows the extended register map.
4
R
0011
Supported port number.
When SUS/RES(71pin)=“1”
0011 : 3 ports
When SUS/RES(71pin)=“0”
Combination with PSEL(66pin) input the supported number of port will be
selected. Please refer to 1.1 Cable Interface Pins.
0001 : 1 port
0010 : 2 port
0011 : 3 port
3
R
010
Indicate the maximum speed that this node supports.
010: 98.304, 196.608 and 393.216 Mbps
4
R
0010
Indicate worst case repeating delay time. 144+(2 x 20)=184 nsec
1 R/W
1
Link active.
1 : Enable
0 : Disable
The logical AND status of this bit and LPS pin.
State will be referred to “L bit” of Self-ID Packet#0.
1 R/W
See
Contender.
Description “1” indicate this node support bus manager function. This bit will be referred
to “C bit” of Self-ID Packet#0.
The reset data is depending on CMC pin setting.
CMC pin condition
1: Pull up (Contender)
0: Pull down (Non Contender)
3
R
010
The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsec
Data Sheet S14452EJ1V0DS00
11
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