XRT91L81 Ver la hoja de datos (PDF) - Exar Corporation
Número de pieza
componentes Descripción
Lista de partido
XRT91L81 Datasheet PDF : 40 Pages
| |||
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
TRANSMITTER SECTION
PRELIMINARY
NAME
LEVEL
TYPE
PIN
DESCRIPTION
TXDI0P
TXDI0N
TXDI1P
TXDI1N
TXDI2P
TXDI2N
TXDI3P
TXDI3N
LVDS
I
H13 Transmit Parallel Data Input
J13 The 622Mbps 4-bit parallel transmit input data should be
K14 applied to the transmitters simultaneously referenced to the ris-
L14 ing edge of the TXCLKI input. The 4-bit parallel interface is
K13
multiplexed into the transmit serial output interface MSB first
(TXDI3P/N).
L13 NOTE: The XRT91L81 can accept 666Mbps 4-bit parallel
M14
transmit input data for Forward Error Correction (FEC)
N14
Applications.
TXCLKIP
TXCLKIN
LVDS
I
H14 Transmit Input Clock
J14 622MHz input clock reference for the 4-bit parallel transmit
input data TXDIP/N[3:0].
NOTE: The XRT91L81 can accept a 666MHz transmit input
clock for Forward Error Correction (FEC) Applications.
TXOP
TXON
CMLDIFF
O
L2 Transmit Serial Data Output
K2 The transmit serial data stream is generated by multiplexing the
4-bit parallel transmit input data into a 2.488Gbps serial data
stream. In Forward Error Correction, the transmit serial data
stream is 2.666Gbps.
TXO2P
TXO2N
CMLDIFF
O
K1 Secondary Transmit Serial Data Output Port
L1 The secondary transmit serial data port can output the TXO
serial data stream or it can output the transmit output clock.
See the pin description of TXO2_SEL and TXO2DIS for more
details.
TXO2_SEL
LVTTL
I
N3 Secondary Transmit Select
Hardware Mode The TXO2_SEL pin is used to determine the
output contents of the secondary transmit serial data output.
"Low" = 2.488Gbit/s Serial Output Data
"High" = Transmit Output Clock (2.488/2.666 GHz)
TXO2DIS
LVTTL
I
N1 Secondary Transmit Disable
Hardware Mode The TXO2DIS pin is used to disable the sec-
ondary transmit serial data output pins. If the secondary trans-
mit serial data is disabled, both TXO2P/N are pulled "High".
"Low" = TXO2 is enabled
"High" = Diabled
REFCLKP
LVPECL
I
REFCLKN
P6 Reference Clock Input
N6 This differential input clock reference is used for the transmit
clock multiplier unit (CMU) to provide the necessary high speed
clock reference for this device. Pin REFFREQSEL determines
the value used as the reference. See Pin REFFREQSEL for
more details.
VCXO_INP
LVPECL
I
VCXO_INN
P4 Voltage Controled Oscillator Input
N4 This differential input clock is used for the transmit PLL jitter
attenuation. Pin REFFREQSEL determines the value used as
the reference. See Pin REFFREQSEL for more details.
6
Share Link: 