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LPC47M112

Enhanced Super I/O Controller with LPC Interface / Dual Game Port Interface

SMSC -> Microchip 

Enhanced Super I/O Controller with LPC Interface

Datasheet

7 POWER FUNCTIONALITY

The LPC47M112 has three power planes: VCC, VTR and VREF.

7.1 VCC Power

The LPC47M112 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational Description Section

and the Maximum Current Values sub-section.

7.2 VTR Support

The LPC47M112 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the

PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description

Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle

Power Functionality and Maximum Current Values sub-sections. If the LPC47M112 is not intended to provide wake-

up capabilities on standby current, VTR can be connected to VCC. VTR powers the IR interface, the PME configuration

registers and the PME interface. The VTR pin generates a VTR Power-on-Reset signal to initialize these components.

Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum

potential at least 10 μs before Vcc begins a power-on cycle. When VTR and Vcc are fully powered, the potential

difference between the two supplies must not exceed 500mV.

7.3 Internal PWRGOOD

An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface

as Vcc cycles on and off. When the internal PWRGOOD signal is “1” (active), Vcc > 2.3V (nominal), and the

LPC47M112 host interface is active. When the internal PWRGOOD signal is “0” (inactive), Vcc ≤ 2.3V (nominal), and

the LPC47M112 host interface is inactive; that is, LPC bus reads and writes will not be decoded.

The LPC47M112 device pins nIO_PME, CLOCKI32, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2 and most GPIOs (as

input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive,

provided VTR is powered. The IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1 and GP61/LED2 pins also remain

active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power

Functionality section. The internal PWRGOOD signal is also used to disable the IR Half Duplex Timeout.

7.4 32.768 kHz Trickle Clock Input

The LPC47M112 utilizes a 32.768 kHz trickle input to supply a clock signal for the fan tachometer logic, LED blink

and wake on specific key function. See the following section for more information.

7.5 Indication of 32kHz Clock

There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M112. This bit is located at

bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR

POR.

Bit[0] (CLK32_PRSN) is defined as follows:

0=32kHz clock is connected to the CLKI32 pin (default)

1=32kHz clock is not connected to the CLKI32 pin (pin is grounded).

Bit 0 controls the source of the 32kHz (nominal) clock for the fan tachometer logic, the LED blink logic and the “wake

on specific key” logic. When the external 32kHz clock is connected, that will be the source for the fan tachometer,

LED and “wake on specific key” logic. When the external 32kHz clock is not connected, an internal 32kHz clock

source will be derived from the 14MHz clock for the fan tachometer, LED and “wake on specific key” logic.

The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is not connected.

These functions will work under VCC power even if the external 32kHz clock is not connected.

ƒ Wake on specific key

ƒ LED blink

ƒ Fan Tachometer

SMSC DS – LPC47M112

Page 17

DATASHEET

Rev. 02-16-07

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