LPC47M112 Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47M112

Enhanced Super I/O Controller with LPC Interface / Dual Game Port Interface

SMSC -> Microchip 

Enhanced Super I/O Controller with LPC Interface

Datasheet

ƒ PME interface block

ƒ PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers)

ƒ “Wake on Specific Key” logic

ƒ LED control logic

ƒ Fan Tachometers

ƒ Pins for PME Wakeup:

- GP42/nIO_PME (output, buffer powered by VTR)

- nRI1 (input)

- GP50/nRI2 (input)

- GP52/RXD2 (input)

- KDAT (input)

- MDAT

- GPIOs (GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, GP61) – all

input-only except GP53, GP60, GP61. See below.

ƒ Other Pins

- IRTX2/GP35 (output, buffer powered by VTR)

- GP53/TXD2(IRTX) (output, buffer powered by VTR)

- GP60/LED1 (output, buffer powered by VTR)

- GP61/LED2 (output, buffer powered by VTR)

7.7 VREF Pin

The LPC47M112 has a reference voltage pin input on pin 44 of the part. This reference voltage can be connected to

either a 5V supply or a 3.3V supply. It is used for the game port. See the “GAME PORT LOGIC” section.

7.8 Maximum Current Values

See the “Operational Description” section for the maximum current values.

The maximum VTR current, ITR, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or

3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by all pins

that are driven by VTR. The pins that are powered by VTR are as follows: GP42 / nIO_PME, IRTX2 / GP35,

GP53/TXD2 (IRTX), GP60 / LED1, GP61 / LED2. These pins, if configured as push-pull outputs, will source a

minimum of 6mA at 2.4V when driving.

The maximum VCC current, ICC, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or

3.3V).

The maximum VREF current, IREF, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or

3.3V).

7.9 Power Management Events (PME/SCI)

The LPC47M112 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt

(SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of

an event to the chipset via the assertion of the nIO_PME output signal on pin 17. See the “PME Support” section.

SMSC DS – LPC47M112

Page 19

DATASHEET

Rev. 02-16-07

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