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RTL8153-CG

INTEGRATED 10/100/1000M ETHERNET CONTROLLER FOR USB APPLICATIONS

Realtek Semiconductor 

RTL8153

Datasheet

6.5. SPI (Serial Peripheral Interface) Flash

SPI Flash is enabled by the RTL8153 through the Chip Select pin, and accessed via a 3-wire interface

consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SPI flash

utilizes an 8-bit instruction register. All instructions, addresses, and data are transferred with the MSB

first and start with a high-to-low transition.

Compared to a parallel bus interface, the Serial Peripheral Interface provides simpler wiring and much

less interaction (crosstalk) among the conductors in the cable. This minimizes the number of conductors,

pins, and the IC package size, reducing the cost of making, assembling, and testing the electronics.

SPI Flash

SO

SI

SCK

CS

Table 18. SPI Flash Interface

Description

Input Data Bus.

Output Data Bus.

SPI Flash Serial Data Clock.

SPI Flash Chip Select.

6.6. Power Management

The RTL8153 complies with ACPI (Rev 1.0, 1.0b, 2.0), Network Device Class Power Management

Reference Specification (V1.0a), such as to support an Operating System-directed Power Management

(OSPM) environment.

The RTL8153 can monitor the network for a Wake-Up Frame or a Magic Packet, and notify the system

via the USB interface when such a packet or event occurs. The system is then restored to a normal state to

process incoming jobs.

When the RTL8153 is in power down mode:

• The RX state machine is stopped. The RTL8153 monitors the network for wake-up events such as a

Magic Packet and Wake-Up Frame in order to wake-up the system. When in power down mode, the

RTL8153 will not reflect the status of any incoming packets in the ISR register and will not receive

any packets into the RX on-chip buffer.

• The on-chip buffer status and packets that have already been received into the RX on-chip buffer

before entering power down mode are held by the RTL8153.

• Transmission is stopped. USB transactions are stopped. The TX on-chip buffer is held.

• After being restored to D0 state, the RTL8153 transmits data that was not moved into the TX on-chip

buffer during power down mode. Packets that were not transmitted completely last time are

re-transmitted.

Integrated 10/100/1000M Ethernet Controller for USB Applications

13

Track ID: JATR-8275-15 Rev. 1.1

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