2961 Ver la hoja de datos (PDF) - Allegro MicroSystems
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Lista de partido
2961
Allegro MicroSystems
2961 Datasheet PDF : 12 Pages
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2961
HIGH-CURRENT
HALF-BRIDGE
PRINTHEAD/MOTOR DRIVER
A logic high on the MODE pin sets the
current-control circuitry into the fast-decay
mode. When the peak current threshold is
detected, the flip-flop is reset and both the
source driver and the sink driver turn OFF.
Load current decays quickly through the
external ground clamp diode, the load, and
the internal flyback diode. In the fast-
decay mode, the OFF time period is one-
half the time that is set by the external RC
network for the slow-decay mode:
tOFF =
RC
2
The amount of ripple current, when
chopping in the fast-decay mode, is
considerably higher than when chopping in
the slow-decay mode.
The frequency of the PWM current
control is determined by the time required
for the load current to reach the set peak
threshold (a function of the load character-
istics and VBB) plus the OFF time of the
switching driver(s) (set by the external RC
components).
To prevent false resetting of the flip-
flop, due to switching transients and noise,
a blanking time for the comparator can be
set by the user where tB ≈ 3600 x C in the
slow-decay mode or tB ≈ 2400 x C in the
fast-decay mode. For C between 100 pF
and 1000 pF, tB is in µs.
POWER CONSIDERATIONS
The UDN2961B/W outputs are opti-
mized for low power dissipation. The sink
driver has a maximum saturation voltage
drop of only 1.4 V at 3.4 A, while the
source driver has a 2.2 V drop at -3.4 A.
Device power dissipation is minimized in
the slow-decay mode, as the chopping
driver (the source driver) is ON for less
than 50% of the chop period. When the
source driver is OFF during a chop cycle,
power is dissipated on chip only by the sink
driver; the rest of the power is dissipated
through the external ground clamp diode.
In the fast-decay mode, the ON time of the
chopping drivers (both the source driver
VREF
INPUT
ENABLE
2940 Ω
±1%
MODE
1
VBB
16
2
15
3
14
CURRENT-
CONTROL
4
LOGIC
13
5
VBB
12
6
11
7
10
8
VCC 9
VBB
47 µF
INPUT
C
1
2
3
4
5
6
C
7
8
R
+5 V
VBB
16
15
CURRENT-
CONTROL
LOGIC
14
13
47 µF
VBB
12
11
VBB
10
VCC 9
+5 V
R
Dwg. EP-038A
and the sink driver) may be greater than 50%, and the power dissipa-
tion will be greater.
GENERAL
A logic low on the ENABLE pin prevents the source driver and the
sink driver from turning ON, regardless of the state of the INPUT pin or
the supply voltages. With the ENABLE pin high, a logic low on the
INPUT pin turns ON the output drivers.
To protect against inductive load voltage transients, an external
ground clamp diode is required. A fast-recovery diode is recom-
mended to reduce power dissipation in the UDN2961B/W. The blank-
ing time prevents false triggering of the current sense comparator,
which can be caused by the recovery current spike of the ground
clamp diode when the chopping source driver turns ON.
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