70P2352-IGT Ver la hoja de datos (PDF) - Unspecified
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70P2352-IGT Datasheet PDF : 42 Pages
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REGISTER DESCRIPTION (CONTINUED)
LEGEND
TYPE
R/O
R/C
DESCRIPTION
Read only
Read and Clear
TYPE DESCRIPTION
R/W Read or Write
78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
Line Rate Selection:
Selects the line rate of all channels as well as the input clock frequency
7
E4
R/W
0
at the CKREFP/N pins.
0: OC-3, STS-3, STM-1 (155.52MHz)
1: E4 (139.264MHz)
6
--
R/W
0
Unused
5
PAR R/W
CKSL
4:3
[1:0]
R/W
Serial/Parallel Interface Selection:
0
Selects the interface to the framer.
0: Serial LVPECL
1: 4-bit Parallel CMOS
Reference Clock Frequency Selection:
Selects the reference clock frequency input at CKREFP/N pins.
11: 155.52MHz / 139.264MHz (differential LVPECL)
XX
10: 77.76MHz / NA (single-ended CMOS)
00: 19.44MHz / 17.408MHz (single-ended CMOS)
Secondary values correspond to E4 frequencies. Default values depend
on the CKSL pin selection upon reset.
2:1
--
R/W
X0 Reserved.
0 SRST R/W
Register Soft-Reset:
0
When this bit is set, all registers are reset to their default values. This
register bit is self-clearing.
Page: 10 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
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