70P2352-IGT Ver la hoja de datos (PDF) - Unspecified

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70P2352-IGT

Dual Channel OC-3/ STM1-E/ E4 LIU

Unspecified 

REGISTER DESCRIPTION

REGISTER ADDRESSING

Address Bits

Bit 7

Bit 6

Bit 5

Assignment

PA[3]

Port Address

PA[2]

PA[1]

Bit 4

PA[0]

78P2352

Dual Channel

OC-3/ STM1-E/ E4 LIU

Bit 3

Bit 2

Bit 1

Sub-Address

SA[2]

SA[1]

SA[0]

Bit 0

Read/

Write

R/W*

REGISTER TABLE

a) PA[3:0] = 0 : Global Registers

Sub

Addr

0

1

2

Reg.

Name

MSCR

(R/W)

INTC

(R/W)

--

(R/W)

Description

Master Control

Interrupt Control

Reserved

Bit 7

E4

<0>

INPOL

<0>

--

<X>

Bit 6

--

<0>

--

<0>

--

<X>

Bit 5

PAR

<0>

--

<1>

--

<X>

Bit 4

Bit 3

CKSL[1]

<X>

--

<0>

--

<X>

CKSL[0]

<X>

--

<0>

--

<X>

Bit 2

--

<X>

--

<X>

--

<X>

Bit 1

--

<X>

MTLOL

<1>

--

<X>

Bit 0

SRST

<0>

MFERR

<1>

--

<0>

b) PA[3:0] = 1, 2 : Port-Specific Registers

Sub

Addr

0

1

2

3

4

5

Reg.

Name

MDCR

(R/W)

SGCR

(R/W)

ACR1

(R/W)

ACR0

(R/W)

MCR2

(R/W)

STAT

(R/C)

Description

Mode Control

Signal Control

Advanced Tx

Control 1

Advanced Tx

Control 0

Mode Control 2

Status Monitor

Bit 7

Bit 6

PDTX

<0>

TCMIINV

<0>

--

<0>

--

<1>

CMI

<1>

--

<X>

PDRX

<0>

RCMIINV

<0>

--

<0>

--

<0>

--

<X>

--

<X>

Bit 5

Bit 4

Bit 3

PMODE

<X>

LOLOR

<0>

--

<0>

--

<1>

--

<X>

--

<X>

SMOD[1] SMOD[0]

<X>

<X>

RLBK LLBK

<0>

<0>

--

--

<0>

<0>

--

--

<0>

<1>

--

--

<0>

<0>

RXLOS RXLOL

<X>

<X>

Bit 2

MON

<0>

RCLKP

<0>

--

<0>

BST[1]

<0>

--

<0>

--

<X>

6-7

-- Reserved

--

--

--

--

--

--

Bit 1

--

<0>

TCLKP

<0>

TPK

<0>

BST[0]

<0>

--

<0>

TXLOL

<X>

--

Bit 0

--

<1>

FRST

<0>

TXEQ

<0>

FLBK

<0>

--

<0>

FERR

<X>

--

Page: 9 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

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