![](/html/AMICC/254367/page29.png)
Figure 19. Serial Input Timing
S
tCHSL
C
tDVCH
D
tSLCH
tCHDX
MSB IN
High Impedance
Q
tCHSH
tSHSL
tSHCH
tCLCH
LSB IN
tCHCL
Figure 20. Write Protect Setup and Hold Timing during WRSR when SRWD=1
W
tSHSL
S
C
tSHWL
A25L80P
D
High Impedance
Q
PRELIMINARY (May 2005, Version 0.0)
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