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A29DL323TV-120

32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

AMIC Technology 

A29DL32x Series

I/O2: Toggle Bit II

The "Toggle Bit II" on I/O2, when used with I/O6, indicates

whether a particular sector is actively erasing (that is, the

Embedded Erase algorithm is in progress), or whether that

sector is erase-suspended. Toggle Bit II is valid after the

rising edge of the final WE pulse in the command sequence.

I/O2 toggles when the system reads at addresses within those

sectors that have been selected for erasure. (The system may

use either OE or CE to control the read cycles.) But I/O2

cannot distinguish whether the sector is actively erasing or is

erase-suspended. I/O6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but cannot

distinguish which sectors are selected for erasure. Thus, both

status bits are required for sector and mode information.

Refer to Table 8 to compare outputs for I/O2 and I/O6.

Figure 6 shows the toggle bit algorithm in flowchart form, and

the section " I/O2: Toggle Bit II" explains the algorithm. See

also the " I/O6: Toggle Bit I" subsection. Figure 20 shows the

toggle bit timing diagram. Figure 21 shows the differences

between I/O2 and I/O6 in graphical form.

Reading Toggle Bits I/O6, I/O2

Refer to Figure 6 for the following discussion. Whenever the

system initially begins reading toggle bit status, it must read

I/O7-I/O0 at least twice in a row to determine whether a toggle

bit is toggling. Typically, a system would note and store the

value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle

bit with the first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system can

read array data on I/O7-I/O0 on the following read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system also

should note whether the value of I/O5 is high (see the section

on I/O5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may

have stopped toggling just as I/O5 went high. If the toggle bit

is no longer toggling, the device has successfully completed

the program or erase operation. If it is still toggling, the device

did not complete the operation successfully, and the system

must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines

that the toggle bit is toggling and I/O5 has not gone high. The

system may continue to monitor the toggle bit and I/O5

through successive read cycles, determining the status as

described in the previous paragraph. Alternatively, it may

choose to perform other system tasks. In this case, the

system must start at the beginning of the algorithm when it

returns to determine the status of the operation (top of Figure

6).

I/O5: Exceeded Timing Limits

I/O5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions I/O5 produces a "1." This is a failure condition that

indicates the program or erase cycle was not successfully

completed.

The device may output a “1” on I/O5 if the system tries to

program a “1” to a location that was previously programmed

to “0.” Only an erase operation can change a “0” back to a

“1.” Under this condition, the device halts the operation, and

when the timing limit has been exceeded, I/O5 produces a

“1.” .

Under both these conditions, the system must write the reset

command to return to reading array data (or to the erase-

suspend-read mode if a bank was previously in the erase-

suspend-program mode).

I/O3: Sector Erase Timer

After writing a sector erase command sequence, the system

may read I/O3 to determine whether or not an erase

operation has begun. (The sector erase timer does not apply

to the chip erase command.) If additional sectors are

selected for erasure, the entire time-out also applies after

each additional sector erase command. When the time-out is

complete, I/O3 switches from "0" to "1." The system may

ignore I/O3 if the system can guarantee that the time

between additional sector erase commands will always be

less than 50µs. See also the "Sector Erase Command

Sequence" section.

After the sector erase command sequence is written, the

system should read the status on I/O7 (Data Polling) or I/O6

(Toggle Bit 1) to ensure the device has accepted the

command sequence, and then read I/O3. If I/O3 is "1", the

internally controlled erase cycle has begun; all further

commands (Except Erase Suspend) are ignored until the

erase operation is complete. If I/O3 is "0", the device will

accept additional sector erase commands. To ensure the

command has been accepted, the system software should

check the status of I/O3 prior to and following each

subsequent sector erase command. If I/O3 is high on the

second status check, the last command might not have been

accepted.

Table 13 shows the status of I/O3 relative to the other status

bits.

PRELIMINARY (May, 2005, Version 0.0)

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AMIC Technology, Corp.

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