A43L8316AV-5.5 Ver la hoja de datos (PDF) - AMIC Technology

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A43L8316AV-5.5

128K X 16 Bit X 2 Banks Synchronous DRAM

AMIC Technology 

A43L8316A

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Symbol

Parameter

CAS

Latency

-5

tRRD(min) Row active to row active delay

3

2

2

tRCD(min) RAS to CAS delay

3

3

2

-

tRP(min) Row precharge time

3

3

2

-

tRAS(min)

Row active time

tRAS(max)

3

8

2

-

3

2

tRC(min) Row cycle time

3

11

2

-

3

tCDL(min) Last data in new col. Address delay

2

tRDL(min) Last data in row precharge

3

2

2

-

3

tBDL(min) Last data in to burst stop

2

3

tCCD(min) Col. Address to col. Address delay

2

3

Number of valid output data

2

Version

-5.5

-6

2

2

3

3

-

-

3

3

-

-

8

7

-

-

100

11

10

-

-

1

2

2

-

-

1

1

2

1

Unit Note

-7

2

CLK

1

3

CLK

1

2

3

CLK

1

2

6

CLK

1

5

µs

9

CLK

1

7

CLK

2

2

CLK

2

2

CLK

2

CLK

CLK

4

CLK

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

(September, 2003, Version 1.0)

8

AMIC Technology, Corp.

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