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A43L8316V

128K X 16 Bit X 2 Banks Synchronous DRAM

AMIC Technology 

A43L8316

Mode Register Filed Table to Program Modes

Register Programmed with MRS

Address

BA

A8

A7

A6

A5

A4

A3

A2

A1

A0

Function RFU

TM

(Note 1) (Note 2)

CAS Latency

BT

Burst Length

Test Mode

CAS Latency

Burst Type

Burst Length

A8 A7

Type

A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0

BT=1

0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0

1

Reserved

01

Vendor

001

-

1 Interleave 0 0 1

2

Reserved

10

Use

010

2

010

4

4

11

Only

011

3

011

8

8

Write Burst Length

1 0 0 Reserved

1 0 0 Reserved Reserved

BA

Length

1 0 1 Reserved

1 0 1 Reserved Reserved

0

Burst

1 1 0 Reserved

1 1 0 Reserved Reserved

1

Single Bit

1 1 1 Reserved

1 1 1 256(Full) Reserved

(Note 3)

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.

Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If BA is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. The full column burst (256bit) is available only at Sequential mode of burst type.

Preliminary (April, 2000, Version 1.0)

10

AMIC Technology, Inc.

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