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A43L2632V-6

1M X 32 Bit X 4 Banks Synchronous DRAM

AMIC Technology 

A43L2632

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Symbol

Parameter

tRRD(min)

tRCD(min)

Row active to row active delay

RAS to CAS delay

Version

-6

-7

12

15

15

15

Unit

Note

ns

1

ns

1

tRP(min)

tRAS(min)

tRAS(max)

tRC(min)

Row precharge time

Row active time

Row cycle time

15

15

42

42

100

63

65

ns

1

ns

1

µs

ns

1

tCDL(min) Last data in new col. Address delay

6

tRDL(min) Last data in row precharge

12

tBDL(min) Last data in to burst stop

6

tCCD(min) Col. Address to col. Address delay

1

7

ns

2

14

ns

2

7

ns

2

1

ns

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

PRELIMINARY (January, 2005, Version 0.0)

9

AMIC Technology, Corp.

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