A45L9332AE-6 Ver la hoja de datos (PDF) - AMIC Technology
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A45L9332AE-6 Datasheet PDF : 55 Pages
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A45L9332A Series
Simplified Truth Table
Command
CKEn-1 CKEn CS
Register
Mode Register Set
Special Mode Register Set H
XL
Refresh
Auto Refresh
Self
Refresh
Entry
Exit
H
H
L
L
L
L
H
H
Bank Active Write Per Bite Disable
& Row Addr. Write Per Bit Enable
H
XL
Read &
Auto Precharge Disable
Column Addr. Auto Precharge Enable
H
XL
Write &
Auto Precharge Disable
Column Addr. Auto Precharge Enable
H
XL
Block Write & Auto Precharge Disable
Column Addr. Auto Precharge Enable
H
XL
Burst Stop
H
XL
Precharge
Bank Selection
Both Banks
H
XL
Clock Suspend or
Active Power Down
Entry
Exit
L
H
L
H
L
HX
Precharge Power Down Mode
Entry
Exit
L
H
L
H
L
L
H
H
DQM
H
No Operation Command
L
H
X
H
RAS CAS
LL
LL
HH
XX
LH
HL
HL
HL
HH
LH
HH
XX
XX
HH
XX
VV
XX
X
HH
XX
WE DSF DQM A10 A9 A8~A0 Notes
L
L
H
X
HL X
OP CODE
X
1,2
1,2,7
3
3
H
3
XX
X
X
3
L
4,5
H
H
X
V Row Addr. 4,5,9
L Column 4
H
L
X
V H Addr. 4,6
L Column 4,5
L
L
X
V H Addr. 4,5,6,9
L Column 4,5
L
H
X
V H Addr. 4,5,6,9
LLX
X
7
VL
L
L
X
XH
X
H
XX
X
X
XXX
H
XX
X
X
VV
X
XX
V
X
8
H
XX
X
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note : 1. OP Code : Operand Code
A0~A10 : Program keys. (@MRS)
Color register exists only one per DQi which both banks share.
So dose Mask Register.
Color or mask is loaded into chip through DQ pin.
2. MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ’s are idle.
A new command can be issued at the next clock of MRS/SMRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
PRELIMINARY (October, 2001, Version 0.1)
10
AMIC Technology, Inc.
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