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A45L9332AE-6 Ver la hoja de datos (PDF) - AMIC Technology

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A45L9332AE-6 Datasheet PDF : 55 Pages
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A45L9332A Series
Summary of 2M Byte SGRAM Basic Features and Benefits
Features
Interface
Bank
Page Depth / 1 Row
Total Page Depth
Burst Length (Read)
Burst Length (Write)
Burst Type
CAS Latency
Block Write
Color Register
Mask Register
Mask function
256K X 32 X 2 SGRAM
Benefits
Better interaction between memory and system without wait-state of
asynchronous DRAM.
Synchronous
High speed vertical and horizontal drawing.
High operation frequency allows performance gain for SCROLL, FILL,
and BitBLT.
Pseudo-infinite row length by on-chip interleaving operation.
2 ea
Hidden row activation and precharge.
256 bit
High speed vertical and horizontal drawing.
2048 bytes
High speed vertical and horizontal drawing
1,2,4,8 Full Page
Programmable burst of 1,2,4,8 and full page transfer per column
addresses.
1,2,4,8 Full Page
Programmable burst of 1,2,4,8 and full page transfer per column
addresses.
BRSW
Switch to burst length of 1 at write without MRS
Sequential & Interleave Compatible with Intel and Motorola CPU based system.
2,3
Programmable CAS latency.
8 Columns
High speed FILL, CLEAR, Text with color registers.
Maximum 32 byte data transfers (e.g. for 8bpp : 32 pixels) with plane
and byte masking functions.
1 ea.
A and B bank share.
1 ea.
Write-per-bit capability (bit plane masking). A and B banks share.
DQM0-3
Byte masking (pixel masking for 8bpp system) for data-out/in
Write per bit
Each bit of the mask register directly controls a corresponding bit
plane.
Pixel Mask at Block Write Byte masking (pixel masking for 8bpp system) for color by DQi
Basic feature And Function Descriptions
1. CLOCK Suspend
1) Click Suspended During Write (BL=4)
CLK
CMD
CKE
Internal
CLK
WR
Masked by CKE
DQ(CL2)
DQ(CL3)
D0
D1
D2
D3
D0
D1
D2
D3
Not Written
Note: CLK to CLK disable/enable=1 clock
2) Clock Suspended During Read (BL=4)
RD
Masked by CKE
Q0
Q1
Q0
Q2
Q3
Q1
Q2
Q3
Suspended Dout
PRELIMINARY (October, 2001, Version 0.1)
18
AMIC Technology, Inc.

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