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A45L9332AF

256K X 32 Bit X 2 Banks Synchronous Graphic RAM

AMIC Technology 

A45L9332A Series

Device Operations (continued)

Bank Activate

The bank activate command is used to select a random row

in an idle bank. By asserting low on RAS and CS with

desired row and bank addresses, a row access is initiated.

The read or write operation can occur after a time delay of

tRCD(min) from the time of bank activation. tRCD(min) is an

internal timing parameter of SGRAM, therefore it is

dependent on operating clock frequency. The minimum

number of clock cycles required between bank activate and

read or write command should be calculated by dividing

tRCD(min) with cycle time of the clock and then rounding off

the result to the next higher integer. The SGRAM has two

internal banks on the same chip and shares part of the

internal circuitry to reduce chip area, therefore it restricts

the activation of both banks immediately. Also the noise

generated during sensing of each bank of SGRAM is high

requiring some time for power supplies recover before the

other bank can be sensed reliably. tRRD(min) specifies the

minimum time required between activating different banks.

The number of clock cycles required between different bank

activation must be calculated similar to tRCD specification.

The minimum time required for the bank to be active to

initiate sensing and restoring the complete row of dynamic

cells is determined by tRAS(min) specification before a

precharge command to that active bank can be asserted.

The maximum time any bank can be in the active state is

determined by tRAS(max). The number of cycles for both

tRAS(min) and tRAS(max) can be calculated similar to tRCD

specification.

Burst Read

The burst read command is used to access burst of data on

consecutive clock cycles from an active row in an active

bank. The burst read command is issued by asserting low

on CS and CAS with WE being high on the positive edge

of the clock. The bank must be active for at least tRCD(min)

before the burst read command is issued. The first output

appears CAS latency number of clock cycles after the issue

of burst read command. The burst length, burst sequence

and latency from the burst read command is determined by

the mode register which is already programmed. The burst

read can be initiated on any column address of the active

row. The address wraps around if the initial address does

not start from a boundary such that number of outputs from

each I/O are equal to the burst length programmed in the

mode register. The output goes into high-impedance at the

end of the burst, unless a new burst read was initiated to

keep the data output gapless. The burst read can be

terminated by issuing another burst read or burst write in

the same bank or the other active bank or a precharge

command to the same bank. The burst stop command is

valid only at full page burst length where the output dose

not go into high impedance at the end of burst and the

burst is wrap around.

Burst Write

The burst write command is similar to burst read command,

and is used to write data into the SGRAM consecutive clock

cycles in adjacent addresses depending on burst length

and burst sequence. By asserting low on CS , CAS and

WE with valid column address, a write burst is initiated.

The data inputs are provided for the initial address in the

same clock cycle as the burst write command. The input

buffer is deselected at the end of the burst length, even

though the internal writing may not have been completed

yet. The writing can not complete to burst length. The burst

write can be terminated by issuing a burst read and DQM

for blocking data inputs or burst write in the same or the

other active bank. The burst stop command is valid only at

full page burst length where the writing continues at the end

of burst and the burst is wrap around. The write burst can

also be terminated by using DQM for blocking data and

precharging the bank “tRDL” after the last data input to be

written into the active row. See DQM OPERATION also.

DQM Operation

The DQM is used to mask input and output operation. It

works similar to OE during read operation and inhibits

writing during write operation. The read latency is two

cycles from DQM and zero cycle for write, which means

DQM masking occurs two cycles later in the read cycle and

occurs in the same cycle during write cycle. DQM operation

is synchronous with the clock, therefore the masking occurs

for a complete cycle. The DQM signal is important during

burst interrupts of write with read or precharge in the

SGRAM. Due to asynchronous nature of the internal write,

the DQM operation is critical to avoid unwanted or

incomplete writes when the complete burst write is not

required. DQM is also used for device selection, byte

selection and bus control in a memory system. DQM0

controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2

controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31.

DQM masks the DQ’s by a byte regardless that the

corresponding DQ’s are in a state of WPB masking or Pixel

masking. Please refer to DQM timing diagram also.

Precharge

The precharge operation is performed on an active bank by

asserting low on CS , RAS , WE and A9 with valid A10 of

the bank to be precharged. The precharge command can

be asserted anytime after tRAS(min) is satisfied from the

bank activate command in the desired bank. “tRP” is defined

as the minimum time required to precharge a bank.

The minimum number of clock cycles required to complete

row precharge is calculated by dividing “tRP” with clock cycle

time and rounding up to the next higher integer. Care

should be taken to make sure that burst write is completed

or DQM is used to inhibit writing before precharge

PRELIMINARY (October, 2001, Version 0.1)

15

AMIC Technology, Inc.

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