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A49LF040TL-33F

4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory

AMIC Technology 

Preliminary

A49LF040

4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory

FEATURES

• Single Power Supply Operation

- Low voltage range: 3.0 V - 3.6 V for Read and Write

Operations

• Standard Intel Low Pin Count Interface

- Read compatible to Intel® Low Pin Count (LPC)

interface

• Memory Configuration

- 512K x 8 (4 Mbit)

• Block Architecture

- 4Mbit: eight uniform 64KByte blocks

- Supports full chip erase for Address/Address

Multiplexed (A/A Mux) mode

• Automatic Erase and Program Operation

- Embedded Byte Program and Block/Chip Erase

algorithms

- Typical 10 µs/byte programming time

- Typical 1s block erase time

• Two Operational Modes

- Low Pin Count Interface (LPC) Mode for in-system

operation

- Address/Address Multiplexed (A/A Mux) Interface

Mode for programming equipment

• Low Pin Count (LPC) Mode

- 33 MHz synchronous operation with PCI bus

- 5-signal communication interface for in-system read

and write operations

- Standard SDP Command Set

- Data# Polling (I/O7) and Toggle Bit (I/O6) features

- 4 ID pins for multi-chip selection

- 5 GPI pins for General Purpose Input Register

- TBL# pin for hardware write protection to Boot Block

- WP# pin for hardware write protection to whole

memory array except Boot Block

• Address/Address Multiplexed (A/A Mux) Mode

- 11-pin multiplexed address and 8-pin data I/O interface

- Supports fast programming on EPROM programmers

- Standard SDP Command Set

- Data# Polling (I/O7) and Toggle Bit (I/O6) features

• Lower Power Consumption

- Typical 12mA active read current

- Typical 24mA program/erase current

• High Product Endurance

- Guarantee 100,000 program/erase cycles for each

block

- Minimum 20 years data retention

• Compatible Pin-out and Packaging

- 32-pin (8 mm x 14 mm) TSOP (TYPE I)

- 32-pin PLCC

GENERAL DESCRIPTION

The A49LF040 flash memory device is designed to be read-

compatible with the Intel Low Pin Count (LPC) Interface

Specification 1.1. This device is designed to use a single low

voltage, range from 3.0 Volt to 3.6 Volt power supply to

perform in-system or off-system read and write operations. It

provides protection for the storage and update of code and

data in addition to adding system design flexibility through

five general-purpose inputs. Two interface modes are

supported by the A49LF040: Low Pin Count (LPC) Interface

mode for In-System programming and Address/Address

Multiplexed (A/A Mux) mode for fast factory programming of

PC-BIOS applications.

The memory is divided into eight uniform 64Kbyte blocks that

can be erased independently without affecting the data in

other blocks. Blocks also can be protected individually to

prevent accidental Program or Erase commands from

modifying the memory. The Program and Erase operations

are executed by issuing the Program/Erase commands into

the command interface by which activating the internal

control logic to automatically process the Program/Erase

procedures. The device can be programmed on a byte-by-

byte basis after performing the Erase operation. In addition to

the Block Erase operation, the Chip Erase feature is provided

in A/A Mux mode that allows the whole memory to be erased

in one single Erase operation. The A49LF040 provides the

status detection such as Data# Polling and Toggle Bit

Functions in both LPC and A/A Mux modes. The process or

completion of Program and Erase operations can be

detected by reading the status bits.

The A49LF040 is offered in 32-lead TSOP and 32-lead

PLCC packages. See Figures 1 and 2 for pin assignments

and Table 1 for pin descriptions.

PRELIMINARY (August, 2004, Version 0.1)

1

AMIC Technology, Corp.

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