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AD6426

Enhanced GSM Processor

Analog Devices 

Preliminary Technical Information

AD6426

TIMING CHARACTERISTICS

Parallel Display Interface

Parameter Comments (see Figure 22)

Min

Typ

Max

Units

t100

LCD Control low width (6 CLKIN cycles)

462

ns

t101

LCD Control high width (6 CLKIN cycles)

462

ns

t102

LCD Control high width read extension (1 CLKIN

77

ns

cycle)

ADD 19:O

DISPLAYCS

RD or HWR

LCDCTL

t100

t101

t102

Figure 22. Parallel Display Interface Timing

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 42 -

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