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AD6650BBC
(Rev.:2003)

Diversity IF-to-Baseband GSM/EDGE Narrow-Band Receiver

Analog Devices 

Preliminary Technical Data

TIMING DIAGRAMS

CLK

tSS

tHS

SYNC

Figure x. SYNC Timing Inputs

TIMING DIAGRAMS – INM Microport Mode

CLK

/RD (/DS)

tS C

/WR (RW)

tHC

tH W R

/CS

A [2 :0 ]

D [7 :0 ]

tSAM

tH A M

Valid Address

tSAM

Valid Data

tH A M

RDY

(/DTACK)

tDRDY

tA C C

Notes:

1. tACC Access time depends on the Address accessed. Access time is measured from FE of /WR to RE of R DY.

tACC requires a maximum of 9 CLK periods

Figure 16. INM Microport Write Timing Requirements.

CLK

/RD (/DS)

tSC

tHC

REV. PrJ 02/27/2003

/WR (RW)

/CS

tSAM

A [2 :0 ]

Valid Address

tZD

tDD

tHA

tZD

D[7:0]

Valid Data

RDY

(/DTACK)

tDRDY

tACC

Notes:

1. tACC Access time depends on the Address accessed. Access time is measured from FE of /WR to RE of RDY.

tACC requires a m axim um of 13 CLK periods and applies to A[2:0]=7,6,5,3,2,1

Figure 17. INM Microport Read Timing Requirements.

10

AD6650

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