AD6652 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Lista de partido
AD6652 Datasheet PDF : 76 Pages
| |||
AD6652
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Table 1.
Parameter
AVDD
VDD
VDDIO
TAMBIENT
Temp
Full
Full
Full
Test Level Min
Typ
IV
2.75
3.0
IV
2.25
2.5
IV
3.0
3.3
IV
−40
+25
Max
Unit
3.3
V
2.75
V
3.6
V
+85
°C
ADC DC SPECIFICATIONS
AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 2.
Parameter (Conditions)
RESOLUTION
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
Input Span = 1 V Internal
Input Span = 2 V Internal
ANALOG INPUT
Input Span = 1.0 V
Input Span = 2.0 V
Input Capacitance
REFERENCE INPUT RESISTANCE
MATCHING CHARACTERISTICS
Offset Error
Gain Error
Temp
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Test Level Min
Typ
Max
Unit
IV
12
Bits
IV
±5
±35
mV
V
0.8
mV
V
±2.5
mV
V
0.1
mV
V
0.54
LSB rms
V
0.27
LSB rms
IV
1
V p-p
IV
2
V p-p
V
7
pF
V
7
kΩ
V
±0.1
% FSR
V
±0.1
% FSR
ADC SWITCHING SPECIFICATIONS
AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 3.
Parameter (Conditions)
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
ACLK Period
ACLK Pulse Width High1
ACLK Pulse Width Low1
DATA OUTPUT PARAMETERS
Wake-Up Time2
OUT-OF-RANGE RECOVERY TIME
Temp
Full
Full
Full
Full
Full
Full
Full
Test Level Min
IV
65
V
V
15.4
V
6.2
V
6.2
V
V
Typ
Max
1
ACLK/2
ACLK/2
2.5
2
Unit
MSPS
MSPS
ns
ns
ns
ms
Cycles
1 Duty cycle stabilizer enabled.
2 Wake-up time is dependent on the value of decoupling capacitors, typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Rev. 0 | Page 5 of 76
Share Link: 