AD73411 Ver la hoja de datos (PDF) - Analog Devices
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AD73411 Datasheet PDF : 36 Pages
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AD73411–SPECIFICATIONS (AVDD = DVDD = VDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, fMCLK = 16.384 MHz,
fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Test Conditions
Min
Typ
Max
Unit
DSP SECTION
VIH
VIH
VIL
VOH
Hi-Level Input Voltage1, 2
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
IDD
Supply Current (Idle)9
IDD
Supply Current (Dynamic)11
CI
Input Pin Capacitance3, 6, 12
CO
Output Pin Capacitance6, 7, 12, 13
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDD max
@ VDD = max
VIN = 0 V
@ VDD = max
VIN = VDD max8
@ VDD = max
VIN = 0 V8
@ VDD = 3.3
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
@ VDD = 3.3
TAMB = 25°C
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = 25°C
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = 25°C
2.0
2.2
2.4
VDD – 0.3
12
11
10
45
43
36
8
8
V
V
0.8
V
V
V
0.4
V
10
µA
10
µA
10
µA
10
µA
mA
mA
mA
mA
mA
mA
pF
pF
NOTES
1 Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2 Input only pins: RESET, BR, DR0, DR1, PWD.
3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
5 Although specified for TTL outputs, all AD73411 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.
6 Guaranteed but not tested.
7 Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
8 0 V on BR.
9 Idle refers to AD73411 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
10 VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
11 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
and Type 6, and 20% are idle instructions.
12Applies to PBGA package type.
13Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
–4–
REV. 0
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