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AD7457
(Rev.:Rev0)

Low Power, Pseudo Differential, 100 kSPS 12-Bit ADC in an 8-Lead SOT-23

Analog Devices 

Table 5. SPORT0 Configuration

Bit

Setting

Comment/Description

ISCLK 1

Serial clock generated internally

SLEN 1111

16 bits of conversion data

RFSR 0

Receive frame sync required every

word

TFSR Don’t care Not used

IRFS 0

RFS is set to be an input and is

generated externally

ITFS

Don’t care Not used

RFSW 1

Alternate receive framing

TFSW Don’t care Not used

INVRFS 0

RFS is active high

INVTFS Don’t care Not used

AD7457

The flag to generate the CS signal is generated by SPORT1. It is

connected to both the ADC and the RFS input of SPORT0 to

provide the frame sync signal for the DSP.

Rev. 0 | Page 15 of 20

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